DocumentCode :
2265136
Title :
A parallel architecture for co-occurrence matrix computation
Author :
Khalaf, S. ; El-Gabali, M. ; Abdelguerfi, M.
Author_Institution :
Dept. of Math., Kuwait Univ., Safat, Kuwait
fYear :
1993
fDate :
16-18 Aug 1993
Firstpage :
945
Abstract :
Using the odd-even network topology, a parallel hardware architecture for gray level image co-occurrence matrix computation is designed. The architecture consists of simple, regularly structured processing elements (PE´s) operating in parallel. As a result, the proposed design is suitable for VLSI implementation. The use of a co-occurrence matrix computational unit of fixed size to handle large images is considered
Keywords :
VLSI; image processing; image texture; parallel architectures; VLSI implementation; co-occurrence matrix computation; computational unit; gray level image; hardware architecture; odd-even network topology; parallel architecture; regularly structured processing elements; Computer architecture; Computer networks; Computer science; Concurrent computing; Hardware; Mathematics; Network topology; Parallel architectures; Pixel; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on
Conference_Location :
Detroit, MI
Print_ISBN :
0-7803-1760-2
Type :
conf
DOI :
10.1109/MWSCAS.1993.343225
Filename :
343225
Link To Document :
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