DocumentCode :
2265219
Title :
Barra: A Parallel Functional Simulator for GPGPU
Author :
Collange, Sylvain ; Daumas, Marc ; Defour, David ; Parello, David
Author_Institution :
ELIAUS-PROMES (UPVD), Perpignan, France
fYear :
2010
fDate :
17-19 Aug. 2010
Firstpage :
351
Lastpage :
360
Abstract :
We present Barra, a simulator of Graphics Processing Units (GPU) tuned for general purpose processing (GPGPU). It is based on the UNISIM framework and it simulates the native instruction set of the Tesla architecture at the functional level. The inputs are CUDA executables produced by NVIDIA tools. No alterations are needed to perform simulations. As it uses parallelism, Barra generates detailed statistics on executions in about the time needed by CUDA to operate in emulation mode. We use it to understand and explore the micro-architecture design spaces of GPUs.
Keywords :
computer graphic equipment; coprocessors; digital simulation; parallel processing; Barra; CUDA executables; GPGPU; NVIDIA tools; Tesla architecture; UNISIM framework; general purpose processing; graphics processing units; native instruction set; parallel functional simulator; Computational modeling; Computer architecture; Graphics processing unit; Hardware; Instruction sets; Load modeling; Registers; CUDA; GPGPU; GPU; UNISIM;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Modeling, Analysis & Simulation of Computer and Telecommunication Systems (MASCOTS), 2010 IEEE International Symposium on
Conference_Location :
Miami Beach, FL
ISSN :
1526-7539
Print_ISBN :
978-1-4244-8181-1
Type :
conf
DOI :
10.1109/MASCOTS.2010.43
Filename :
5581577
Link To Document :
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