VLSI implementation of a feature mapping neural network

Modification of Kohonen´s self-organizing feature map algorithm and its dedicated parallel hardware implementation are the focus of this paper. This work is motivated by the need to implement a 5×5 neural network using digital standard cells and high level VLSI system design tools. The neural net considered is a two layered, feed forward architecture that learns relationships among unknown input data patterns. The prototype system consists of 25 processing units (neurons). Each processing unit operates at 10 MHz. Communication among processing units is accomplished using a broadcast bus. Performance of the system is estimated to be 110,000 iterations per second