Title :
A high speed and low power on CMOS/SOI technology and its modelings
Author :
Lee, M. ; Asada, K.
Author_Institution :
Dept. of Electron. Eng., Tokyo Univ., Japan
Abstract :
Reduction of parasitic capacitances has predicted two-time high speed in deep-submicron CMOS/SIMOX ring oscillators (RO), where measurements are plotted for comparison with an analytical model with ultra-thin SOI film thickness of 30-nm and 50-nm. Analytical lower bounds for power dissipations of a CMOS/SOI inverter using a time-dependent capacitance model and the conventional model are propounded. It is concluded that (1) noticable results show high speed (24 ps/stage at the gate length of 0.15-μm and supply voltage of 2.0 V) at 50-nm SOI-film thick and very low power (6 μW/stage at the gate length, Lg, of 0.2-μm and supply voltage, Vdd, of 1.5 V) at 30-nm SOI-film thick CMOS/SOI ring oscillator, while models at 30-nm SOI-film as poly-Si gate thickness decreases predicted comparable high speed (24 ps/stage at Lg=0.1-μm with Vdd=2.5 V) like 50-nm SOI-film devices. This is promising for high performance of deep-submicron gate ultra-thin film CMOS/SOI technology at low voltage operations
Keywords :
CMOS integrated circuits; SIMOX; integrated circuit modelling; integrated circuit technology; 0.1 micron; 0.15 micron; 2 V; 2.5 V; 30 nm; 50 nm; CMOS/SOI inverter; CMOS/SOI technology; Si; high speed operation; low power operation; low voltage operation; modeling; poly-Si gate thickness; power dissipation; time-dependent capacitance model; ultra-thin SOI film thickness; Analytical models; CMOS technology; Capacitance measurement; Parasitic capacitance; Power dissipation; Ring oscillators; Semiconductor device modeling; Thickness measurement; Velocity measurement; Voltage-controlled oscillators;
Conference_Titel :
Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on
Conference_Location :
Detroit, MI
Print_ISBN :
0-7803-1760-2
DOI :
10.1109/MWSCAS.1993.343260