DocumentCode :
2265608
Title :
An efficient hardware accelerator for power grid simulation
Author :
Hashizume, Taiki ; Sugano, Hisako ; Nishizawa, Shinichi ; Yoshikawa, Masaya ; Fukui, Masahiro
Author_Institution :
Grad. Sch. of Sci. & Eng., Ritsumeikan Univ., Kusatsu, Japan
fYear :
2009
fDate :
24-27 May 2009
Firstpage :
2994
Lastpage :
2997
Abstract :
With the deep submicron technologies, IR drop and electromigration have become remarkable by decreasing of the power supply voltage. Therefore, power grid optimization becomes important to achieve the stable operation of large scale integration (LSI). However, it requires large computation time. In this paper, we propose a novel power grid simulation technique which can be applied to a large scale power grid. The proposal technique achieves ldquohigh speed processing by hardware acceleratorrdquo and ldquorealization of high accuracy computation with fixed point arithmeticrdquo. The proposed power grid simulation algorithm achieves 32 times more high speed processing than software processing. The accuracy is proven by experimental comparison with SPICE simulation.
Keywords :
VLSI; fixed point arithmetic; power engineering computing; power grids; power integrated circuits; LSI; SPICE simulation; deep submicron technologies; electromigration; fixed point arithmetic; hardware accelerator; large scale integration; power grid simulation; power supply voltage; software processing; Acceleration; Computational modeling; Electromigration; Hardware; Large scale integration; Large-scale systems; Power grids; Power supplies; Proposals; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
Type :
conf
DOI :
10.1109/ISCAS.2009.5118432
Filename :
5118432
Link To Document :
بازگشت