DocumentCode
2265643
Title
Nonlinear SC network analysis and synthesis for image processing
Author
Seidel, Mark N.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
fYear
1993
fDate
16-18 Aug 1993
Firstpage
1052
Abstract
The author advances a general theory of analysis and synthesis of steady-state nonlinear switched-capacitor (SC) networks. The approach relies on steady-state behavior, and addresses several issues raised in the literature, such as the impact of surrounding circuitry, appropriate clock phasing, exactness of network solutions, and interconnection rules. A new nonlinear SC element is proposed that enables the synthesis of networks of arbitrary two-terminal voltage-controlled nonlinear resistors
Keywords
analogue processing circuits; image processing; nonlinear network analysis; nonlinear network synthesis; switched capacitor networks; clock phasing; image processing; interconnection rules; network analysis; network synthesis; nonlinear SC network; nonlinear switched-capacitor networks; steady-state behavior; steady-state nonlinear networks; two-terminal voltage-controlled nonlinear resistors; Circuit synthesis; Clocks; Fuses; Image analysis; Image processing; Network synthesis; Performance analysis; Resistors; Steady-state; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on
Conference_Location
Detroit, MI
Print_ISBN
0-7803-1760-2
Type
conf
DOI
10.1109/MWSCAS.1993.343264
Filename
343264
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