• DocumentCode
    2265644
  • Title

    Hardware architecture for high-accuracy real-time pedestrian detection with CoHOG features

  • Author

    Hiromoto, Masayuki ; Miyamoto, Ryusuke

  • Author_Institution
    Grad. Sch. of Inf., Kyoto Univ., Kyoto, Japan
  • fYear
    2009
  • fDate
    Sept. 27 2009-Oct. 4 2009
  • Firstpage
    894
  • Lastpage
    899
  • Abstract
    Co-occurrence histograms of oriented gradients (CoHOG) is a powerful feature descriptor for pedestrian detection. However, its calculation cost is large because the feature vector for the CoHOG descriptor is very high-dimensional. In this paper, in order to achieve real-time detection on embedded systems, we propose a novel hardware architecture for the CoHOG feature extraction. Our architecture exploits high degree of fine-grained parallelism and adopts an efficient histogram generator combined with a linear SVM classifier. The proposed architecture is implemented on a Xilinx Virtex-5 FPGA and it achieves real-time pedestrian detection on 38 fps 320×240 video. That is more than 100 times faster than the execution on a state-of-the-art Intel CPU.
  • Keywords
    embedded systems; feature extraction; object detection; support vector machines; CoHOG feature extraction; Xilinx Virtex-5 FPGA; cooccurrence histograms; embedded systems; fine-grained parallelism; hardware architecture; high-accuracy real-time pedestrian detection; linear SVM classifier; oriented gradients; realtime detection; Computer vision; Costs; Embedded system; Feature extraction; Field programmable gate arrays; Hardware; Histograms; Real time systems; Support vector machine classification; Support vector machines;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Vision Workshops (ICCV Workshops), 2009 IEEE 12th International Conference on
  • Conference_Location
    Kyoto
  • Print_ISBN
    978-1-4244-4442-7
  • Electronic_ISBN
    978-1-4244-4441-0
  • Type

    conf

  • DOI
    10.1109/ICCVW.2009.5457609
  • Filename
    5457609