DocumentCode :
2265695
Title :
Low-complexity multi-purpose IP Core for quantized Discrete Cosine and integer transform
Author :
Sun, Chi-Chia ; Donner, Philipp ; Götze, üJrgen
Author_Institution :
Inf. Process. Lab., Dortmund Univ. of Technol., Dortmund, Germany
fYear :
2009
fDate :
24-27 May 2009
Firstpage :
3014
Lastpage :
3017
Abstract :
In this paper a low-complexity and highly-integrated IP core for image/video transformations is presented. It is possible to perform quantized 8times8 DCT and quantized 8times8/4times4 integer transforms on the presented reconfigurable architecture using only shift and add operations. The XVID experimental and FPGA synthesis results show that the proposed architecture not only achieves multiplierless video transformations efficiently, but also retains good transformation quality. It is worth noticing that the proposed IP Core is very suitable for low-complexity and multi-purpose video CODECs in SoC designs.
Keywords :
discrete cosine transforms; field programmable gate arrays; quantisation (signal); system-on-chip; video codecs; video coding; FPGA synthesis; SoC designs; image-video transformations; low-complexity multi-purpose IP core; multiplierless video transformations; quantized discrete cosine-integer transform; reconfigurable architecture; video CODEC; Computational complexity; Discrete cosine transforms; Discrete transforms; Field programmable gate arrays; Information processing; Quantization; Reconfigurable architectures; Sun; Video codecs; Video compression; CORDIC; DCIT; DCT; FPGA; QDCIT; QDCT; integer transform; low power; reconfigurable architecture;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
Type :
conf
DOI :
10.1109/ISCAS.2009.5118437
Filename :
5118437
Link To Document :
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