Towards an optimal trade-off of Viterbi Decoder Design

Viterbi decoder (VD) is widely used in modern communication systems. For low power applications, trace-back approach (TBA) is usually employed for the survivor memory unit (SMU) of VD. However, TBA suffers from long latency and low throughput. Employing multiple memory banks can resolve the throughput issue on a great extent. In this paper, we present efficient schemes to improve the latency issue of conventional TBA by exploiting pre-trace-back method. In the meantime, we adopt buffer-based TBA method to reduce memory access times, thus reduce power assumption significantly. Simulation results show that the proposed decoding schemes cause either zero or negligible performance loss.