Title :
Design of a 64-bit low-energy high-performance adder using dynamic feedthrough logic
Author :
Chuang, Pierce ; Li, David ; Sachdev, Manoj
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada
Abstract :
In this work, a new design approach in implementing low-energy, high-performance 64-bit adder using dynamic feedthrough logic (DFTL) is introduced and analyzed. Design issues of using DFTL in several logic depth are analyzed in order to achieve the best optimal balance between performance and power consumption. A ldquotiming windowrdquo technique is also proposed to reduce the amount of excessive power dissipation in the DFTL approach. A 64-bit Sklansky carry-merge adder is used as a benchmark comparison between different logic styles including DFTL, CDL, dynamic, and static logic. Simulation results reveal that the proposed work achieves better performance and is more energy efficient than the other logic styles for high performance adder designs.
Keywords :
adders; carry logic; integrated circuit design; logic design; low-power electronics; Sklansky carry-merge adder; dynamic feedthrough logic; logic depth; logic design; low-energy high-performance adder; power consumption; power dissipation; static logic; timing window; word length 64 bit; CMOS logic circuits; CMOS technology; Energy consumption; Logic design; Logic gates; Low voltage; MOS devices; MOSFETs; Performance analysis; Timing;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5118443
