An asynchronously embedded datapath for performance acceleration and energy efficiency

Motivated by the unwillingness to accept the worst-case timing constraint that synchronous logic imposes, and additionally motivated by finding a supply voltage scaling scheme for datapath circuits that is unconstrained by timing errors in memory elements, the authors have built an asynchronous datapath that is embedded seamlessly into a synchronous register file. This paper will show that not only does asynchronous arithmetic logic exhibit many characteristics that allow it to be inherently lower power, but it is significantly faster than any synchronous counterpart and is a perfect candidate technology for datapath acceleration. Further, novel circuits are presented that allow asynchronous datapath units to be embedded in a synchronous environment with little overhead while the dual-rail asynchronous encoding scheme is successfully converted with equally low overhead. The authors have built a test chip being fabricated at the time of publication. The circuits on this chip will be discussed and simulation results given showing this design to be both energy and performance efficient when compared to other known datapath designs.