DocumentCode
2265920
Title
Current-mode multiple-valued dynamic memory
Author
Khodabndehloo, Golnar ; Mirhassani, Mitra ; Ahmadi, Majid
Author_Institution
Electr. & Comput. Eng., Univ. of Windsor, Windsor, ON, Canada
fYear
2009
fDate
24-27 May 2009
Firstpage
3058
Lastpage
3061
Abstract
In this paper, a multiple-valued DRAM is proposed. Error correction has been used to increase the noise margin of the system. The refresh system is based on series configuration of A/D and D/A converters for each data line. The A/D converters are based on a modular reduction operation, which provides an area efficient design. This memory cell can be used in hardware implementation of multiple valued neural networks.
Keywords
DRAM chips; analogue-digital conversion; digital-analogue conversion; error correction; neural nets; A-D converters; D-A converters; DRAM; current-mode multiple-valued dynamic memory; error correction; modular reduction operation; multiple valued neural networks; Capacitors; Error correction; Error correction codes; Leakage current; Neural network hardware; Neural networks; Noise reduction; Power supplies; Random access memory; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location
Taipei
Print_ISBN
978-1-4244-3827-3
Electronic_ISBN
978-1-4244-3828-0
Type
conf
DOI
10.1109/ISCAS.2009.5118448
Filename
5118448
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