• DocumentCode
    2265943
  • Title

    HSK: A Hierarchical Parallel Simulation Kernel for Multicore Platform

  • Author

    Wenjie, Tang ; Yao, Yiping

  • Author_Institution
    Dept. of Comput. Sci., Nat. Univ. of Defense Technol., Changsha, China
  • fYear
    2011
  • fDate
    26-28 May 2011
  • Firstpage
    19
  • Lastpage
    24
  • Abstract
    The development of CPU has stepped into the era of multi-core. Due to lack of support on thread level, most of the simulation platform can not take full advantage of multicore. To fulfill this gap, we proposed a hierarchical parallel simulation kernel(HSK) model. The model has two layers. The first layer, named process kernel, was responsible for managing all thread kernels on second layer. The second layer is a group of thread kernels, which were responsible for scheduling and advancing logical processes. Each thread kernel was mapped onto an executing thread to advance simulation parallel. In addition, two algorithms were proposed to support high performance: (1) To improve the communication efficiency between threads, we proposed a pointer-based communication mechanism. By using buffers, synchronization between threads can be annihilated. (2) To eliminate redundant Lower Bound on Time Stamp(LBTS) computation and not to interrupt thread execution, we employ an approximate method to compute LBTS asynchronously. A proof of validity was presented. The execution performance of HSK was demonstrated by a series of simulation experiments with a modified phold model. The HSK can achieve good speedup for applications, especially with coarse-grained event.
  • Keywords
    multi-threading; multiprocessing systems; parallel processing; processor scheduling; synchronisation; CPU; HSK model; LBTS computation; asimulation parallel; buffers; coarse-grained event; communication efficiency; executing thread; execution performance; hierarchical parallel simulation kernel; logical processes; multicore platform; pointer-based communication mechanism; process kernel; proof of validity; redundant lower bound on time stamp computation; scheduling; simulation platform; synchronization; thread execution; thread kernels; thread level; Computational modeling; Instruction sets; Kernel; Multicore processing; Object oriented modeling; Parallel processing; hierarchical simulation kernel; multicore; parallel discrete event simulation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel and Distributed Processing with Applications (ISPA), 2011 IEEE 9th International Symposium on
  • Conference_Location
    Busan
  • Print_ISBN
    978-1-4577-0391-1
  • Electronic_ISBN
    978-0-7695-4428-1
  • Type

    conf

  • DOI
    10.1109/ISPA.2011.42
  • Filename
    5951876