DocumentCode :
2265944
Title :
Real Exposed temperature evaluation using reordering of implanted amorphous Si layers
Author :
Shibata, Satoshi ; Nambu, Yoshihiro ; Izutani, H. ; Morita, Takahito ; Yamazawa, K. ; Arai, Manabu
Author_Institution :
Matsushita Electr. Ind. Co. Ltd., Toyama, Japan
fYear :
2003
fDate :
30 Sept.-2 Oct. 2003
Firstpage :
339
Lastpage :
342
Abstract :
In this paper, we present an indirect method to evaluate the Really Exposed temperature and uniformity within a wafer during an thermal process between 450°C to 580 °C using reordering of implanted Amorphous Si Layers (REAL method). We show two different examples of low temperature processing where REAL was used to measure the actual wafer temperature: Co Silicidation and plasma CVD. The silicidation example shows how REAL can be used to accurately and practically monitor RTP equipment and processes. For plasma CVD, we demonstrate, for the first time, the actual wafer temperature during processing. Through this study, it can be said that the new temperature monitoring method has been established.
Keywords :
amorphous semiconductors; elemental semiconductors; metallisation; plasma CVD; rapid thermal processing; semiconductor growth; semiconductor thin films; silicon; temperature measurement; 450 to 580 degC; Co silicidation; RTP; Si; implanted amorphous Si layers; plasma CVD; rapid thermal processing; real exposed temperature evaluation; temperature monitoring; thermal process; wafer temperature; Amorphous materials; Calibration; Plasma measurements; Plasma temperature; Spectroscopy; Temperature measurement; Temperature sensors; Thickness measurement; Time measurement; Toy industry;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Semiconductor Manufacturing, 2003 IEEE International Symposium on
ISSN :
1523-553X
Print_ISBN :
0-7803-7894-6
Type :
conf
DOI :
10.1109/ISSM.2003.1243296
Filename :
1243296
Link To Document :
بازگشت