DocumentCode
2266193
Title
A Priority-Aware NoC to Reduce Squashes in Thread Level Speculation for Chip Multiprocessors
Author
Dai, Wenbo ; An, Hong ; Li, Qi ; Li, Gongming ; Deng, Bobin ; Wu, Shilei ; Li, Xiaomei ; Liu, Yu
Author_Institution
Sch. of Comput. Sci. & Technol., Univ. of Sci. & Technol. of China, Hefei, China
fYear
2011
fDate
26-28 May 2011
Firstpage
87
Lastpage
92
Abstract
Thread Level Speculation (TLS) is a technique aims at boosting the performance of sequential programs running on Chip Multiprocessors (CMPs) by automatically parallelizing them. It exempts programmers from the heavy task of parallel programming. But its performance may suffer from frequent squashing caused by inter-thread data dependency violation. In this paper, we propose a Network-on-Chip (NoC) in CMP that employs a priority-aware packet arbitration policy. Packet scheduling guided by such policy reduces the occurrence of TLS squashes. Simulation results with 5 applications show that our policy reduces squashes by 22% in best case and 15% on average. Moreover, our priority aware approach could be generalized to similar scenarios in which different threads running on CMP manifest different priorities.
Keywords
microprocessor chips; multi-threading; network-on-chip; chip multiprocessor; inter-thread data dependency violation; network-on-chip; packet scheduling; parallel programming; priority-aware NoC; priority-aware packet arbitration policy; sequential program; squashes reduction; thread level speculation; Art; Instruction sets; Nickel; Protocols; Scalability; Switches; network on chip; prioirity; squash; thread level speculation;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Processing with Applications (ISPA), 2011 IEEE 9th International Symposium on
Conference_Location
Busan
Print_ISBN
978-1-4577-0391-1
Electronic_ISBN
978-0-7695-4428-1
Type
conf
DOI
10.1109/ISPA.2011.21
Filename
5951888
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