An error correcting decoder implemented as a digital neural network with a new clocking scheme

A digital neural network decoder for a three bit error correcting code with block length 64 has been built. Balanced code words make correction of more than three bit errors possible. A dynamically changing threshold function allows parallel updating of the neurons in the Hopfield structured network. This method is faster than the serial approach and has better error correction abilities than a fixed step function in fully parallel mode. A prototype network running at 50 MHz has been built with a new clocking technique. When cascading eight pipelined nets on a chip we expect error correction at 12 Gbit/s at a clock frequency of 200 MHz