Metrics and design considerations on the energy-delay tradeoff of digital circuits

In this paper, general metrics of the energy-delay (E-D) tradeoff in digital VLSI circuits are discussed. More specifically, the general class of metrics EⁱD^j with arbitrary exponents is adopted and evaluated for various commercial microprocessors. Results indicate that practical circuits are designed by minimizing a wider range of metrics compared to the ED or ED² metrics usually assumed in the literature. Hence, the general metrics EⁱD^j describes the energy-delay tradeoff in a more realistic way. An interesting interpretation of the adopted metrics is provided to gain an insight into the relationship between energy and delay in energy-efficient designs. Various properties are also derived analytically by resorting to the logical effort method. Simulations on a 65-nm technology are performed to exemplify and validate the theoretical results.