Novel low voltage current-mirror sense amplifier based Flip-Flop with reduced delay time

Author

Cao, Tuan Vu ; Wisland, Dag T. ; Moradi, Farshad ; Lande, Tor Sverre

Author_Institution

Dept. of Inf., Univ. of Oslo, Blindern, Norway

fYear

2009

fDate

24-27 May 2009

Firstpage

3166

Lastpage

3169

Abstract

A new current-mirror sense-amplifier based flip-flop (CMSA-FF) for ultra-low voltage applications is presented in this paper. The better performance of the proposed flip-flop at ultra-low voltage (down to 120 mV) can be achieved by reducing the number of stacked transistors from VDD to GND compared to conventional SAFFs. The speed improvement of CMSA-FF is also obtained by reducing the discharging time and the setup time/hold time of the pulse generator stage as well as the delay of the set-reset (SR) latch stage. This reduces the clock to output delay time of the CMSA-FF by 56.94 %, and the setup/hold time window smaller and closer to the clock trigger edge. The proposed flip-flop is implemented in a 65 nm CMOS technology.

Keywords

CMOS integrated circuits; current mirrors; flip-flops; low-power electronics; pulse generators; CMOS technology; clock trigger edge; current-mirror sense amplifier; flip-flop; pulse generator; reduced delay time; set-reset latch stage; setup time/hold time; size 65 nm; stacked transistors; ultra-low voltage applications; CMOS technology; Circuits; Clocks; Delay effects; Flip-flops; Frequency; Low voltage; Metastasis; Propagation delay; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

Conference_Location

Taipei

Print_ISBN

978-1-4244-3827-3

Electronic_ISBN

978-1-4244-3828-0

Type

conf

DOI

10.1109/ISCAS.2009.5118475

Filename

5118475