Title :
SRAM voltage and current sense amplifiers in sub-32nm double-gate CMOS insensitive to process variations and transistor mismatch
Author :
Nasalski, Piotr ; Makosiej, Adam ; Giraud, Bastien ; Vladimirescu, Andrei ; Amara, Amara
Author_Institution :
DMCS, Tech. Univ. of Lodz (T.U.L), Lodz, Poland
Abstract :
This paper presents a comparative study of two novel sub-32 nm current (CSA) and voltage (VSA) sense amplifiers in fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. The proposed sense amplifiers (SA) need 40% to 4 times less power, achieve a 10-15% increase in speed and have a 2.5 to 5 times larger tolerance to Vth and L mismatch compared to published DG SAs. Both architectures take advantage of the back gate in order to improve circuit properties. The new CSA is 12% faster and reduces power consumption 3.3 times compared to the new VSA, with the latter having a significant advantage in size.
Keywords :
CMOS integrated circuits; SRAM chips; amplifiers; silicon-on-insulator; transistor circuits; SRAM voltage; circuit property; current sense amplifier; double-gate CMOS; fully depleted double-gate silicon-on-insulator; power consumption; process variation; size 32 nm; transistor mismatch; voltage sense amplifier; CMOS process; Capacitance; Circuits; Energy consumption; Monte Carlo methods; Paper technology; Power amplifiers; Random access memory; Silicon on insulator technology; Voltage;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5118476
