Title :
Boolean factoring of logic functions
Author :
Caruso, Giuseppe
Author_Institution :
Dipartimento di Ingegneria Elettrica, Palermo Univ., Italy
Abstract :
This paper presents an algorithm for Boolean factoring. The general strategy of it is similar to the one used by an algorithm for algebraic factoring. This carries out the factoring process by recursively applying three basic operations called expansion, selection and reduction. The new algorithm achieves Boolean factoring using a novel expansion procedure that generates Boolean products by exploiting the notion of elementary rectangle
Keywords :
Boolean functions; logic CAD; multivalued logic circuits; Boolean factoring; elementary rectangle; expansion procedure; factoring process; logic functions; multilevel logic synthesis; Cascading style sheets; Costs; Logic functions; Power capacitors;
Conference_Titel :
Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on
Conference_Location :
Detroit, MI
Print_ISBN :
0-7803-1760-2
DOI :
10.1109/MWSCAS.1993.343342
