Algorithm-based error detection for signal processing applications on a hypercube multiprocessor

Author

Balasubramanian, Vijay ; Banerjee, Prithviraj

Author_Institution

Illinois Univ., Urbana, IL, USA

fYear

1989

fDate

5-7 Dec 1989

Firstpage

134

Lastpage

143

Abstract

In many cases, it may be possible to redesign parallel algorithms so as to provide a low-cost online scheme for hardware error detection without any hardware modifications. This approach is called algorithm-based error detection. Two useful computations in signal processing are analyzed: QR factorization and singular-value decomposition. For each of these applications, numerous ways of applying algorithm-based error detection using different system-level encoding strategies are investigated. Different schemes have been observed to result in varying error coverages and time overheads. The results of studies performed on a 16-processor Intel iPSC-2/D4/MX hypercube multiprocessor are reported

Keywords

computerised signal processing; encoding; error detection; fault tolerant computing; parallel algorithms; 16-processor Intel iPSC-2/D4/MX; QR factorization; algorithm based error detection; hypercube multiprocessor; parallel algorithms; signal processing applications; singular-value decomposition; system-level encoding; Application software; Computer errors; Concurrent computing; Fast Fourier transforms; Fault detection; Hardware; Hypercubes; Matrix decomposition; Signal processing algorithms; Singular value decomposition;

fLanguage

English

Publisher

ieee

Conference_Titel

Real Time Systems Symposium, 1989., Proceedings.

Conference_Location

Santa Monica, CA

Print_ISBN

0-8186-2004-8

Type

conf

DOI

10.1109/REAL.1989.63564

Filename

63564