Incremental I/O planning with white space redistribution for flip-chip design

The flip-chip package gives the highest chip density of any packaging method to support the pad-limited ASIC design. One of the most important characteristics of flip-chip designs is that the input/output buffers could be placed anywhere inside a chip. We need to focus on not only the assignment of I/O bumps, but also the cost for placing I/O buffer blocks into the design. In this paper, we first introduce the incremental floorplanning problem for the flip-chip design in which the white space of the packings can be optimized to favor the insertion of I/O buffers. So that the initial packing results can be migrated to be matched up with the flip-chip package pattern without sacrificing much of the previous optimization in the original designs. We then present min cost flow based algorithms for I/O buffer insertion which optimize the I/O assignment in terms of interconnect cost. The experimental results have shown that our algorithm can improve wirelength by about 20% while the Power/Groud(P/G) buffers and signal I/O buffers are distributed more evenly.