A new concept for accurate modeling of VLSI interconnections and its application for timing simulation

Author

Wunder, Bernhard ; Lehmann, G. ; Muller-Glaser, Klaus D.

Author_Institution

Inst. fur Tech. der Inf., Karlsruhe Univ., Germany

fYear

1996

fDate

16-20 Sep 1996

Firstpage

72

Lastpage

77

Abstract

This paper presents a new concept for accurately modeling the timing behavior of VLSI interconnections using frequency domain methods and taking into consideration distributed parasitics as well as lumped elements and contact holes. A piecewise linear signal representation is used to catch the waveform dependencies of submicron structures. The models are applied in an analysis tool for clock trees and in a concept for accurate post-layout timing simulation

Keywords

VLSI; circuit CAD; circuit analysis computing; integrated circuit interconnections; timing; VLSI interconnections; distributed parasitics; frequency domain methods; piecewise linear signal representation; post-layout timing simulation; timing simulation; Clocks; Delay estimation; Frequency domain analysis; Integrated circuit interconnections; Logic; Parasitic capacitance; Propagation delay; Switching circuits; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1996, with EURO-VHDL '96 and Exhibition, Proceedings EURO-DAC '96, European

Conference_Location

Geneva

Print_ISBN

0-8186-7573-X

Type

conf

DOI

10.1109/EURDAC.1996.558186

Filename

558186