Hardware implementation of a novel inference engine for interval type-2 fuzzy control on FPGA

Interval type-2 fuzzy logic controllers (IT2 FLCs) have shown a promising potential in handling uncertainties compared to their type-1 counterparts, and as a result, we have witnessed increasing usage of IT2 FLCs in various applications. Due to the complex structures of IT2 FLCs, using them in real-time applications might be computationally expensive. To facilitate real-time implementation of these controllers, hardware with parallel processing abilities are recommended; field-programmable gate arrays (FPGA) are one class of such hardware. In this paper, we propose a structure for implementing a new IT2 FLC inference mechanism called BMM [2] - that has been recently introduced in the literature - on an FPGA. We first demonstrated how the proposed structure can be implemented on software; next, we proposed an implementation architecture for the IT2 FLC mechanism on hardware. We performed simulations and experiments on two different plants and compared the speed of our controllers. The performance speed as well as the tracking of our proposed control structure in simulations and experiments were shown to be very close to each other. Using the BMM engine for the proposed hardware structure proves to be faster than other existing controllers in the literature. Thus, it is expected that IT2 FLCs can be easily implemented on hardware to further enable their real-time applications.