Embedded CMOS SRAM for an ASIC implementation of a satellite communication transmultiplexer

The proposed all-digital transmultiplexer organized for 800 voice channels is defined as a filter module followed by an FFT module; it operates at a 36 MHz data rate. The functional organization and timing of the Polyphase Filter is described. Design of a subunit, the Data Stage Module, as a single chip was done as an example of ASIC implementation; it includes two 800×8 SRAMs, one 800×8 ROM, and two 8-bit multipliers. The SRAMs are custom designs; the others are standard library cells. Four modem techniques are incorporated into the RAM design. Three of them including the look-ahead bit-line equalizing and precharging method, the divided-word-line method, and the sense amplifier output and data bus equalizing method are used to gain speed and reduce power dissipation. A write enable transition detecting method is used to allow consecutive read and write operations at the same address; this tailors the design to this specific application