DocumentCode
2267223
Title
System design optimization for MCM
Author
Franzon, Paul D. ; Stanaski, Andrew ; Tekmen, Yusuf ; Banerjai, Sanjeev
Author_Institution
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
fYear
1995
fDate
31 Jan-2 Feb 1995
Firstpage
138
Lastpage
143
Abstract
Many performance/cost advantages can be gained if a chip-set is optimally redesigned to take advantage of the high wire density, fast interconnect delays, and high pin-counts available in MCM-D/flip-chip technology. Examples are given showing for what conditions the cost of the system can be reduced through chip partitioning and how the performance/cost of a computer core can be increased by 81%
Keywords
circuit optimisation; delays; flip-chip devices; integrated circuit interconnections; integrated circuit packaging; multichip modules; wiring; MCM-D/flip-chip technology; chip partitioning; high wire density; interconnect delays; performance/cost advantages; system design optimization; Circuit testing; Clocks; Cost function; Delay; Design optimization; Logic; Packaging; Pins; Read-write memory; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Multi-Chip Module Conference, 1995. MCMC-95, Proceedings., 1995 IEEE
Conference_Location
Santa Cruz, CA
Print_ISBN
0-8186-6970-5
Type
conf
DOI
10.1109/MCMC.1995.512017
Filename
512017
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