Title :
High-performance/small-area multipliers for use in digital filtering applications
Author :
Kwentus, Alan Y. ; Hung, Hing-Tsun ; Willson, Alan N., Jr.
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Abstract :
A multiplier architecture and encoding scheme well suited for programmable digital filtering applications is described. The multiplier´s partial product recoding scheme uses only simple multiplexers and takes advantage of a RAM that stores filter coefficients. We use an optimized 20-transistor full-adder cell in the carry-save adder array, and a carry-select vector-merge adder produces the final output. An integrated circuit comprising an 11-bit by 11-bit multiplier using second order recoding has been fabricated in 2-μm CMOS technology. It operates in 22 ns and its core occupies 1.53 mm2. Also, an 11-bit by 16-bit multiplier using third order recoding has been fabricated through MOSIS in 1.2-μm CMOS technology. Its core occupies 0.9 mm2 and it operates in 19 ns
Keywords :
CMOS logic circuits; digital arithmetic; digital filters; encoding; multiplying circuits; programmable filters; 1.2 micron; 19 ns; 2 micron; 22 ns; CMOS technology; MOSIS; RAM; carry-save adder array; carry-select vector-merge adder; digital filtering applications; encoding scheme; filter coefficients storage; full-adder cell; integrated circuit; multiplexers; multiplier architecture; partial product recoding scheme; programmable digital filter; second order recoding; small-area multipliers; third order recoding; Adders; CMOS integrated circuits; CMOS technology; Digital filters; Digital signal processing; Encoding; Filtering; Hardware; Integrated circuit technology; Multiplexing;
Conference_Titel :
Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on
Conference_Location :
Detroit, MI
Print_ISBN :
0-7803-1760-2
DOI :
10.1109/MWSCAS.1993.343396
