Title :
Design and implementation of an area and time efficient systolic parallel Booth multiplier
Author :
Panneerselvam, G. ; Nowrouzian, B.
Author_Institution :
Dept. of Electr. & Comput. Eng., Calgary Univ., Alta., Canada
Abstract :
This paper presents combined area-efficient and time-efficient systolic architectures for parallel Booth multiplication. These systolic architectures employ composite (instead of fine grained) cells in order to optimize the silicon area and latency. The complexity of the composite cell is controllable by choosing the proper input size. The composite cell design takes advantages of algorithmic improvements within the cell. These cells are connected only to the neighbors
Keywords :
MOS logic circuits; ULSI; digital arithmetic; multiplying circuits; systolic arrays; MOS IC; ULSI; area-efficient systolic architectures; composite cell design; systolic parallel Booth multiplier; time-efficient systolic architectures; Adders; Computer architecture; Delay; Integrated circuit interconnections; MOSFETs; Parasitic capacitance; Silicon; Ultra large scale integration; Very large scale integration; Wire;
Conference_Titel :
Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on
Conference_Location :
Detroit, MI
Print_ISBN :
0-7803-1760-2
DOI :
10.1109/MWSCAS.1993.343398
