Design of a new compact and regular 8×8 multiplier using redundant binary number representation

A new compact and highly regular redundant binary multiplier employing SD number representation has been developed. The n-bit multiplication time required by the multiplier is proportional to log ₂n. A modified redundant to-binary converter has also been proposed, which results in a reduction of the delay time and size of the multiplier. The multiplier adopts a hybrid V-L adder tree structure. The modified Booth´s algorithm is employed to reduce the number of partial products to half. For an 8×8 multiplier employing the modified converter, the chip size is 2096×3256 μm². The multiplication time is measured as 48.9 ns using a 2 μm design rule. We estimated the multiplication time of a 16×16 multiplier to be 70 ns using a 2 μm design rule, and about 35 ns using a 1 μm design rule and double layer metal wiring. The estimation of the delay time of a 32×32 multiplier is about 70 ns using a 1 μm design rule and double layer metal wiring