Title :
Proceedings of the 8th International Conference on VLSI Design
Abstract :
The following topics were dealt with: routing; hardware-software design and CAD; sequential automatic test pattern generation; field programmable gate arrays; high-level synthesis; combinational automatic test pattern generation; logic synthesis and retiming; VLSI arithmetic; decay testing; chip design; image compression; analog circuit test; synthesis and verification; VLSI technology; testability; low-power and analog design; array processor design; diagnosis and self-checking; floorplanning and partitioning; design for testability
Keywords :
VLSI; analogue integrated circuits; built-in self test; circuit CAD; circuit layout CAD; delays; design for testability; digital arithmetic; fault diagnosis; field programmable gate arrays; high level synthesis; integrated circuit design; integrated circuit testing; logic CAD; logic design; logic partitioning; logic testing; network routing; parallel processing; sequential circuits; timing; CAD; VLSI arithmetic; VLSI design; VLSI technology; analog circuit test; analog design; array processor design; chip design; combinational automatic test pattern generation; decay testing; design for testability; fault diagnosis; field programmable gate arrays; floorplanning and partitioning; hardware-software design; high-level synthesis; image compression; logic retiming; logic synthesis; low power design; routing; self-checking; sequential automatic test pattern generation; testability; verification;
Conference_Titel :
VLSI Design, 1995., Proceedings of the 8th International Conference on
Conference_Location :
New Delhi, India
Print_ISBN :
0-8186-6905-5
DOI :
10.1109/ICVD.1995.512067
