DocumentCode
2268239
Title
Synthesis from mixed specifications
Author
Mooney, V.J. ; Coelho, C.N. ; Sakamoto, Takanori
Author_Institution
Comput. Syst. Lab., Stanford Univ., CA
fYear
1996
fDate
16-20 Sep 1996
Firstpage
114
Lastpage
119
Abstract
We present a hardware synthesis system that accepts system-level specifications in both Verilog HDL and C. A synchronous semantics is assumed for both languages in order to guarantee a uniform underlying model. The rationale for mixed input specifications is to support hardware/software co-design by allowing the migration to hardware of system modules originally described in the C language. We discuss assumptions and limitations of the input description style, a high-level synthesis system, and the application of such a system to some design examples
Keywords
hardware description languages; high level synthesis; logic CAD; C; C language; Verilog HDL; hardware synthesis system; hardware/software co-design; high-level synthesis; mixed specifications; synchronous semantics; Application software; Computer languages; Control system synthesis; Costs; Design automation; Embedded software; Flow graphs; Hardware design languages; High level synthesis; Software tools;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1996, with EURO-VHDL '96 and Exhibition, Proceedings EURO-DAC '96, European
Conference_Location
Geneva
Print_ISBN
0-8186-7573-X
Type
conf
DOI
10.1109/EURDAC.1996.558192
Filename
558192
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