Title :
Multithreaded vector architectures
Author :
Espasa, Roger ; Valero, Mateo
Author_Institution :
Dept. d´´Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
Abstract :
The purpose of this paper is to show that multi-threading techniques can be applied to a vector processor to greatly increase processor throughput and maximize resource utilization. Using a trace driven approach, we simulate a selection of the Perfect Club and Specfp92 programs and compare their execution time on a conventional vector architecture with a single memory port and on a multithreaded vector architecture. We devote an important part of this paper to study the interaction between multi-threading and main memory latency. This paper focuses on maximizing the usage of the memory port, the most expensive resource is typical vector computers. A study of the cost associated with the duplication of the vector register file is also carried out. Overall, multithreading provides for this architecture a performance advantage of more than a factor of 1.4 for realistic memory latencies, and can drive the utilization of the single memory port as high as 95%
Keywords :
discrete event simulation; parallel architectures; performance evaluation; vector processor systems; Perfect Club; Specfp92 programs; main memory latency; multithreaded vector architectures; performance advantage; processor throughput; resource utilization; trace driven approach; vector processor; vector register file; Computer aided instruction; Computer architecture; Costs; Delay; Multithreading; Parallel processing; Registers; Resource management; Throughput; Yarn;
Conference_Titel :
High-Performance Computer Architecture, 1997., Third International Symposium on
Conference_Location :
San Antonio, TX
Print_ISBN :
0-8186-7764-3
DOI :
10.1109/HPCA.1997.569677