DocumentCode
2268459
Title
Polysilicon gate depletion effect on deep-submicron circuit performance
Author
Lin, Wallace W. ; Liang, Chunlin
Author_Institution
Intel Corp., Santa Clara, CA, USA
fYear
1994
fDate
5-6 Jun 1994
Firstpage
185
Lastpage
188
Abstract
By integrating the efforts in process, device and circuit simulations, this paper investigates the polysilicon-gate depletion effect (PDE) on performance of circuits composed of deep-submicron transistors. The DC and AC components of PDE on circuit performance are separated for the first time. The study delineates quantitatively the competing effect between the DC and AC PDE. Results of this study suggest the following: (i) PDE degrades circuit speed through dominance of the DC component in the competing effect. Reduction of gate oxide thickness lessens this DC PDE dominance behavior. (ii) Circuit speed degradation due to PDE becomes more significant during low-power operation. (iii) The above phenomenon in (ii) can be substantially improved by thinning the gate oxide thickness
Keywords
CMOS integrated circuits; MOSFET; circuit analysis computing; elemental semiconductors; integrated circuit modelling; semiconductor device models; silicon; AC components; CMOS IC; DC components; MOSFET; circuit simulation; circuit speed degradation; deep-submicron circuit performance; deep-submicron transistors; device simulation; gate oxide thickness; low-power operation; polysilicon-gate depletion effect; Capacitance; Circuit optimization; Circuit simulation; Data mining; Degradation; Delay effects; Doping; FETs; Ring oscillators; Semiconductor device modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
Numerical Modeling of Processes and Devices for Integrated Circuits, 1994. NUPAD V., International Workshop on
Conference_Location
Honolulu, HI
Print_ISBN
0-7803-1867-6
Type
conf
DOI
10.1109/NUPAD.1994.343461
Filename
343461
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