Title :
PLA based synthesis and testing of hazard free logic
Author :
Bhattacharyya, U.K. ; Gupta, I. Sen ; Nath, S. Shyama ; Dutta, P.
Author_Institution :
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
Abstract :
This paper presents a divide and conquer approach for the hazard-free realization of combinational networks. The circuit is partitioned into a set of supergates which are individually made hazard-free. Since each supergate has to be implemented in two-level form, the circuit can be implemented as a multilevel network of PLAs. A modified supergate partitioning for multi-output circuits has also been proposed. Experiments to evaluate the testability of the synthesized circuits have been carried out
Keywords :
combinational circuits; design for testability; hazards and race conditions; logic CAD; logic partitioning; logic testing; programmable logic arrays; PLA based synthesis; combinational networks; hazard free logic; multi-output circuits; multilevel network; supergate partitioning; testability; testing; Circuit synthesis; Circuit testing; Combinational circuits; Computer science; Delay effects; Hazards; Input variables; Logic testing; Programmable logic arrays; System testing;
Conference_Titel :
VLSI Design, 1995., Proceedings of the 8th International Conference on
Conference_Location :
New Delhi
Print_ISBN :
0-8186-6905-5
DOI :
10.1109/ICVD.1995.512089
