CMOS-SRAM soft-error simulation system

Author

Satoh, Shigeo ; Sudo, Ritsuo ; Tashiro, Hiroko ; Higaki, Naoshi ; Yamaguchi, Seiichirou ; Nakayama, Noriaki

Author_Institution

Fujitsu Labs. Ltd., Atsugi, Japan

fYear

1994

fDate

5-6 Jun 1994

Firstpage

181

Lastpage

184

Abstract

We present a soft-error simulation system for designing CMOS-SRAM cells. We proposed a new noise current model and combined it with the SRAM´s equivalent circuit. Using a three-dimensional topography simulator and considering the Rutherford scattering, we obtained the exact injection probability. The simulation results agree with those from a compulsory exposure experiment. Our system predicts the field soft-error rate from the alpha-particle emission rate, mask layout, and process conditions

Keywords

CMOS memory circuits; Rutherford backscattering; SRAM chips; alpha-particle effects; circuit analysis computing; digital simulation; equivalent circuits; errors; integrated circuit modelling; integrated circuit noise; probability; surface topography; 3D topography simulator; CMOS SRAM cells; Rutherford scattering; alpha-particle emission rate; field soft-error rate; injection probability; mask layout; noise current model; process conditions; soft-error simulation system; static RAM equivalent circuit; Alpha particles; Circuit noise; Circuit simulation; Circuit testing; Equivalent circuits; Low-frequency noise; MOSFETs; Predictive models; Semiconductor device modeling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Numerical Modeling of Processes and Devices for Integrated Circuits, 1994. NUPAD V., International Workshop on

Conference_Location

Honolulu, HI

Print_ISBN

0-7803-1867-6

Type

conf

DOI

10.1109/NUPAD.1994.343462

Filename

343462