DocumentCode
2268528
Title
A new switching-level approach to multiple-output functions synthesis
Author
Bolchini, Cristiana ; Buonanno, Giacomo ; Sciuto, Donatella ; Stefanelli, Renato
Author_Institution
Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
fYear
1995
fDate
4-7 Jan 1995
Firstpage
125
Lastpage
129
Abstract
A new methodology for multiple-output functions synthesis at transistor level is presented. The final network produces the defined output values by creating a set of connections among source, ground and output nodes not necessarily implementing specific subcircuits constituting each single function. Area minimization and timing constraints are figures of merit for the quality of the proposed solution. Application results for a set of randomly generated functions are also reported
Keywords
CMOS logic circuits; circuit layout CAD; integrated circuit layout; logic CAD; minimisation of switching nets; multivalued logic circuits; area minimization; figures of merit; multiple-output functions synthesis; randomly generated functions; switching-level; timing constraints; transistor level; Circuit synthesis; Cost function; Design optimization; Joining processes; Logic design; MOSFETs; Minimization; Network synthesis; Programmable logic arrays; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1995., Proceedings of the 8th International Conference on
Conference_Location
New Delhi
ISSN
1063-9667
Print_ISBN
0-8186-6905-5
Type
conf
DOI
10.1109/ICVD.1995.512090
Filename
512090
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