Title :
A new switching-level approach to multiple-output functions synthesis
Author :
Bolchini, Cristiana ; Buonanno, Giacomo ; Sciuto, Donatella ; Stefanelli, Renato
Author_Institution :
Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
Abstract :
A new methodology for multiple-output functions synthesis at transistor level is presented. The final network produces the defined output values by creating a set of connections among source, ground and output nodes not necessarily implementing specific subcircuits constituting each single function. Area minimization and timing constraints are figures of merit for the quality of the proposed solution. Application results for a set of randomly generated functions are also reported
Keywords :
CMOS logic circuits; circuit layout CAD; integrated circuit layout; logic CAD; minimisation of switching nets; multivalued logic circuits; area minimization; figures of merit; multiple-output functions synthesis; randomly generated functions; switching-level; timing constraints; transistor level; Circuit synthesis; Cost function; Design optimization; Joining processes; Logic design; MOSFETs; Minimization; Network synthesis; Programmable logic arrays; Timing;
Conference_Titel :
VLSI Design, 1995., Proceedings of the 8th International Conference on
Conference_Location :
New Delhi
Print_ISBN :
0-8186-6905-5
DOI :
10.1109/ICVD.1995.512090
