DocumentCode
2268603
Title
Fully asynchronous, robust, high-throughput arithmetic structures
Author
Patra, P. ; Fussell, D.S.
Author_Institution
Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
fYear
1995
fDate
4-7 Jan 1995
Firstpage
141
Lastpage
145
Abstract
This paper presents some novel circuit designs for bit serial adders and multipliers built out of some unusual, but well-defined circuit primitives. The circuits are fully delay-insensitive, provide good reliability and speed, and are easily verified. The structures are flexible and handle inputs of arbitrary lengths while being asymptotically optimal in speed and area. The scaleability of these circuits makes them. Very attractive for applications such as RSA cryptosystems which need very large operands and fast multiplication
Keywords
VLSI; adders; asynchronous circuits; digital arithmetic; integrated logic circuits; multiplying circuits; RSA cryptosystems; bit serial adders; bit serial multipliers; delay-insensitive; fully asynchronous structures; high-throughput arithmetic structures; scaleability; Adders; Arithmetic; Asynchronous circuits; Clocks; Delay; Public key cryptography; Robustness; Switches; Throughput; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1995., Proceedings of the 8th International Conference on
Conference_Location
New Delhi
ISSN
1063-9667
Print_ISBN
0-8186-6905-5
Type
conf
DOI
10.1109/ICVD.1995.512093
Filename
512093
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