A graph approach to DFT hardware placement for robust delay fault BIST

In order to test a ULSI circuit robustly and less expensively for delay faults we proposed a robust delay-fault built-in self-testing model. Long pattern simulation times and excessive hardware overhead have been a concern in our model. We propose a graph heuristic to optimally place Design for Testability (DFT) hardware in order to eliminate hazards in TEST mode. This technique produces a circuit structure that is hazard free for any single-bit changing sequence and reduces the CPU time drastically as we avoid pattern simulation. We collapse the new PI´s and PO´s added to the circuit and this reduces the hardware overhead significantly