• DocumentCode
    2268827
  • Title

    Wave pipelined architecture folding: a method to achieve low power and low area

  • Author

    Ghosh, Debabrata ; Nandy, S.K.

  • Author_Institution
    SGS-Thomson, New Delhi, India
  • fYear
    1995
  • fDate
    4-7 Jan 1995
  • Firstpage
    184
  • Abstract
    Futuristic portable real-time personal communication systems demand low power and high performance simultaneously. This poses a serious challenge to the designers since low power and high performance are two conflicting requirements. In this paper we propose a method called Wave Pipelined Architecture Folding (WPAF) which can be used effectively to reduce power while maintaining the operational throughput. WPAF exploits logic style and architecture along with the clock-free wave pipelining scheme to achieve low power. The technique comes with an additional advantage of reduced chip area which is important from the cost point of view
  • Keywords
    VLSI; digital integrated circuits; integrated circuit design; logic design; pipeline processing; chip area reduction; clock-free wave pipelining scheme; low power design; wave pipelined architecture folding; Adders; Clocks; Costs; Logic; Pipeline processing; Power dissipation; Real time systems; Registers; Solid state circuits; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 1995., Proceedings of the 8th International Conference on
  • Conference_Location
    New Delhi
  • ISSN
    1063-9667
  • Print_ISBN
    0-8186-6905-5
  • Type

    conf

  • DOI
    10.1109/ICVD.1995.512102
  • Filename
    512102