A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 μm CMOS technology

The effect of using an n-guardring compared to p-guardring in preventing latchup due to remote transient at drain of I/O buffer n-channel transistor for 0.8 μm CMOS technology is studied. Steady state simulations performed using a 2D device simulator TMA-MEDICI, show that the n-guardring is more effective compared to the p-guardring in increasing the remote trigger level for latchup. It is found that an increase in substrate resistance increased the remote trigger current level for latchup