Toward the automatic synthesis of process flows for semiconductor devices

In this paper we describe the implementation of a fabrication process flow synthesizer for semiconductor devices. The synthesizer takes a geometrical description of the cross-section of a device as input and outputs all possible planar fabrication processes to construct it. The synthesis problem is solved by representing the device structure as a directed acyclic graph and finding its corresponding set of linear extensions, thus establishing a feasible design space. The synthesizer uses an internal database of processes, etchants, and materials to calculate process parameters such as etchant selection selectivities and diffusion times, and selects the process flow with the maximum yield