DocumentCode :
2268989
Title :
Computing area and wire length efficient routes for channels
Author :
Pal, Rajat Kumar ; Pal, Sudebkumar Prasant ; Das, Madan Mohan ; Pal, Ajit
Author_Institution :
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
fYear :
1995
fDate :
4-7 Jan 1995
Firstpage :
196
Lastpage :
201
Abstract :
The first stage in channel routing is that of computing a routing solution S, for a given channel with as few tracks as possible. We consider a second stage in which it is desirable to reduce the total wire length without increasing area of routing. In this paper we propose efficient polynomial time algorithms for appreciably reducing the total wire length in two-, three- and multi-layer routing solutions by permuting tracks in the solution S obtained in the first stage. This results in a routing solution that is economical in terms of area as well as total wire length. Our algorithms are particularly important in practical terms since the problem of minimizing the total wire length in a routing solution is NP-hard
Keywords :
VLSI; circuit layout CAD; computational complexity; integrated circuit layout; minimisation; network routing; NP-hard; VLSI layout; area efficient routes; channel routing; multilayer routing solutions; polynomial time algorithms; total wire length reduction; wire length efficient routes; Computer industry; Computer science; Costs; Councils; Hazards; Minimization methods; Polynomials; Routing; Wire; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 1995., Proceedings of the 8th International Conference on
Conference_Location :
New Delhi
ISSN :
1063-9667
Print_ISBN :
0-8186-6905-5
Type :
conf
DOI :
10.1109/ICVD.1995.512108
Filename :
512108
Link To Document :
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