Testability-oriented channel routing

Author

Khare, J. ; Mitra, Sujoy ; Nag, K. ; Maly, W. ; Rutenbar, R.

Author_Institution

Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

fYear

1995

fDate

4-7 Jan 1995

Firstpage

208

Lastpage

213

Abstract

The quality of IC testing can be improved by applying appropriate design strategies. In this paper, we present a testability-oriented routing methodology, which can be used to modify the IC layout so as to reduce the probability of test escape. A testability-oriented iterative channel routing tool based on this methodology has been developed. Example applications of this tool illustrating the methodology are also presented in the paper

Keywords

circuit layout CAD; circuit optimisation; design for testability; fault diagnosis; integrated circuit layout; integrated circuit testing; integrated circuit yield; network routing; IC layout modification; IC testing quality; WrenTR; bridging fault; design strategies; fault detectability; fault undetectability; iterative channel routing tool; test escape probability; testability-oriented channel routing; yield loss; Cost function; Fault detection; Integrated circuit layout; Integrated circuit testing; Iterative methods; Manufacturing; Modems; Routing; Semiconductor device manufacture; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1995., Proceedings of the 8th International Conference on

Conference_Location

New Delhi

ISSN

1063-9667

Print_ISBN

0-8186-6905-5

Type

conf

DOI

10.1109/ICVD.1995.512110

Filename

512110