DocumentCode :
2269352
Title :
FPGA based design of Generic Multilevel Built In Test Equipment for radars
Author :
Roy, Taniza ; Marndi, Subhasis ; Jadia, Kaushal
Author_Institution :
LRDE, DRDO, Bangalore, India
fYear :
2012
fDate :
7-11 May 2012
Abstract :
Built In Test Equipments are used to simulate targets to check functionality of different subsystems and the performance (like ECCM) of the radar as a whole. We present an Field Programmable Gate Array (FPGA) based design of a Generic Multilevel Built In Test Equipment (BITE) capable of simulating target echo at Intermediate Frequency (IF), Radio Frequency (RF) levels and at Field. The design also closely simulates the target behavior, like motion in range and azimuth, different doppler, different modulation codes and multiple targets. The implementation solution presented utilizes the efficient FPGA resources so as to meet the timings in crucial applications. The work highlights the features of the design with real implementation and test in a radar system.
Keywords :
built-in self test; electronic countermeasures; field programmable gate arrays; radar equipment; BITE; ECCM; FPGA-based design; field programmable gate array; generic multilevel built-in test equipment; intermediate frequency level; modulation codes; radar system; radio frequency level; target behavior; target echo simulation; Doppler radar; Field programmable gate arrays; Frequency modulation; Radio frequency; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Radar Conference (RADAR), 2012 IEEE
Conference_Location :
Atlanta, GA
ISSN :
1097-5659
Print_ISBN :
978-1-4673-0656-0
Type :
conf
DOI :
10.1109/RADAR.2012.6212241
Filename :
6212241
Link To Document :
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