Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering

In this paper we present new techniques to reduce the power consumption of a static CMOS circuit by enlarging transistors in high fan-out gates and reordering inputs to the gates. The techniques are developed based on observations from results of hspice simulations. These methods are incorporated into a performance and power constrained module generator, PowerSizer. Experimental results from the module generator on several real circuits show that as much as 15% saving in power consumption can be obtained on arithmetic circuits with almost no tradeoff in area or delay