Design of a VLSI parallel processor for fuzzy computing

Author

Ascia, G. ; Catania, V.

Author_Institution

Istituto di Inf. e Telecommun., Catania Univ., Italy

fYear

1995

fDate

4-7 Jan 1995

Firstpage

315

Lastpage

320

Abstract

The paper presents the design of a VLSI fuzzy processor which is capable of performing fuzzy inferences based on the α-level sets theory. The use of the α-level sets family to represent fuzzy sets allows a considerable saving of memory resources if compared with conventional fuzzy inference methods which use membership functions to represent fuzzy sets. The main features of the architecture presented are parallelism and scalability. The processor comprises a set of units which work parallelly and asynchronously to process the various rules. The structure is easy to scale up, as an increase in the number of processing units does not produce bottlenecks in performance. The performance obtainable is about 300 KFLIPS, with a clock frequency of 50 MHz, 8 input variables, either crisp or fuzzy, and an 8 bit resolution

Keywords

VLSI; fuzzy logic; fuzzy set theory; inference mechanisms; integrated circuit design; microprocessor chips; parallel architectures; α-level sets theory; 50 MHz; 8 bit; VLSI parallel processor; clock frequency; fuzzy computing; fuzzy inferences; membership functions; memory resources; parallelism; processing units; scalability; Clocks; Concurrent computing; Frequency; Fuzzy set theory; Fuzzy sets; Input variables; Parallel processing; Scalability; Set theory; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1995., Proceedings of the 8th International Conference on

Conference_Location

New Delhi

ISSN

1063-9667

Print_ISBN

0-8186-6905-5

Type

conf

DOI

10.1109/ICVD.1995.512131

Filename

512131