Design of a highly reconfigurable interconnect for array processors

Different interconnection topologies have different desirable properties and different algorithms run best on different networks. If the network topology is reconfigurable, it can be tailored to suit the particular algorithm being executed. Reconfigurability of processor arrays is also important from fault-tolerance point of view. An array processor that is programmable by the user any number of times to yield a different topology or to isolate faults is envisaged in this paper. The system has a host or controller that broadcasts a command to the interconnect to configure itself into a particular fashion. The interconnect uses static-RAM programming technology and can be programmed to different configurations by sending a different set of bits to the configuration RAM in the interconnect. We present three designs reconfigurable into array, ring, mesh, or Illiac mesh topologies. The first design is reconfigurable to different topologies, but provides no redundancy or fault tolerance. The second and third designs are capable of graceful degradation by eliminating faulty elements