A VLSI architecture for the computation of NURBS patches

Author

Gopi, Meenakshi Sundaram ; Manohar, Swami

Author_Institution

Supercomput. Educ. & Res. Centre, Indian Inst. of Sci., Bangalore, India

fYear

1995

fDate

4-7 Jan 1995

Firstpage

326

Lastpage

331

Abstract

B-Spline curves and patches are increasingly being used in several areas of computer graphics and geometric modeling. The rationalized counterpart of B-spline called Non-Uniform Rational B-Spline (NURBS) is invariably used in all the present day geometric modeling packages. For an interactive modeling session, thousands of NURBS patches have to be computed and drawn per second. Such performance is beyond the reach of even the most advanced workstations available today. Advances in hardware support for parametric curve and patch generation have thus acquired increased importance. The authors give a complete hardware solution for the generation of NURBS patches

Keywords

VLSI; computational geometry; parallel architectures; splines (mathematics); B-spline curves; NURBS patches; VLSI architecture; complete hardware solution; computer graphics; geometric modeling; interactive modeling session; nonuniform rational B-spline; patch generation; Computer architecture; Computer graphics; Hardware; Packaging; Solid modeling; Spline; Surface reconstruction; Surface topography; Very large scale integration; Workstations;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1995., Proceedings of the 8th International Conference on

Conference_Location

New Delhi

ISSN

1063-9667

Print_ISBN

0-8186-6905-5

Type

conf

DOI

10.1109/ICVD.1995.512133

Filename

512133