VLSI floorplan generation and area optimization using AND-OR graph search

Floorplan design based on rectangular dualization is considered in two phases. First, given the adjacency graph and sets of aspect ratios of the blocks, a topology is generated which is likely to yield a minimum-area floorplan during the second phase of optimal sizing. Since the problem of finding such topology seems to be intractable, a heuristic search method using AND-OR graphs is employed in the top-down first phase. Novel heuristic estimates are used to reduce the search effort. For slicing topologies, a bottom-up polynomial-time algorithm is used to solve the second phase. Moreover, the first phase is able to report inherently nonslicible floorplans. The proposed method outperforms the existing techniques, as evident from the experimental results