DocumentCode
2269884
Title
Resource requirements for field programmable interconnection chips
Author
Bhatia, Dinesh ; Haralambides, J.
Author_Institution
Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
fYear
1995
fDate
4-7 Jan 1995
Firstpage
376
Lastpage
380
Abstract
In this paper we prove an Ω(n log n) lower bound on the number of edges of an n-permutation graph G=(V, E). The lower bound is applicable to and characterizes permutations for Field Programmable Interconnection Chips and, more importantly, permutation networks in general. We also propose a family of permutation networks as a variation of the known Benes network with a wide range of diameters, a network property directly related to routing delays. Finally, the relation between the total number of programmable switches and the routing delay (maximum length of routing paths for specific I/O permutations) is explored
Keywords
VLSI; graph theory; integrated circuit interconnections; network routing; Benes network; VLSI; field programmable interconnection chips; n-permutation graph; network property; permutation networks; programmable switches; routing delays; routing paths; specific I/O permutations; user-configured interconnection; Computer architecture; Delay; Design automation; Genetic mutations; Joining processes; Network topology; Pins; Routing; Switches; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1995., Proceedings of the 8th International Conference on
Conference_Location
New Delhi
ISSN
1063-9667
Print_ISBN
0-8186-6905-5
Type
conf
DOI
10.1109/ICVD.1995.512142
Filename
512142
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